1. Field of the Invention
The present invention relates to a method for forming vias in a substrate, and more particularly to a method for forming an insulation layer on the side wall of vias in a substrate by using polymer.
2. Description of the Related Art
FIGS. 1 to 3 show schematic views of a conventional method for forming vias in a substrate. First, referring to FIG. 1, a substrate 1 is provided. The substrate 1 has a first surface 11 and a second surface 12. Afterward, a plurality of grooves 13 are formed on the first surface 11 of the substrate 1. An insulation layer 14 is then formed on the side wall of the grooves 13 by chemical vapor deposition, and a plurality of accommodating spaces 15 are formed. The material of the insulation layer 14 is usually silicon dioxide.
Referring to FIG. 2, the accommodating spaces 15 are filled with a conductive metal 16. The material of the conductive metal 16 is usually copper. Finally, the first surface 11 and the second surface 12 of the substrate 1 are ground or etched so as to expose the conductive metal 16, as shown in FIG. 3.
In the conventional method, the insulation layer 14 is formed by chemical vapor deposition, so that the thickness of the insulation layer 14 on the side wall of the grooves 13 is limited, and is usually under 0.5 μm. Moreover, the thickness of the insulation layer 14 on the side wall of the grooves 13 is not uniform, that is, the thickness of the insulation layer 14 on the upper side wall of the grooves 13 is not exactly equal to that on the lower side wall of the grooves 13. Thus, the electrical capacity is not uniform.
Therefore, it is necessary to provide an innovative and advanced method for forming vias in a substrate to solve the above problems.